Aspects disclosed herein relate to processing systems designed to handle virtual addresses. More specifically, aspects disclosed herein relate to precise and efficient invalidation mechanisms for virtually tagged structures, such as a virtually indexed virtually tagged (VIVT) cache.
Virtual memory extends physical memory space and improves the efficiency of sharing the physical memory among applications, processors, and other entities of a processing system. A virtual address is used to address the virtual memory space, which is divided into blocks of contiguous virtual memory addresses, or “pages.” Software programs may be written with reference to virtual addresses, while for execution of program instructions by the processors, a translation of the virtual addresses to physical address may be performed.
Memory management units (MMUs) may be used for looking up page tables which map virtual addresses to corresponding physical addresses to obtain translations of the virtual addresses to physical addresses, a process referred to as a “page table walk.” Page table walks are often time consuming, so MMUs may include hardware such as a translation lookaside buffer (TLB) to cache translations for frequently accessed pages. The TLB may be implemented as a tagged hardware lookup table, which is tagged using the virtual addresses. Thus, if a virtual address hits in the TLB (i.e., there is a matching tag in the TLB for the virtual address), the corresponding physical address translation may be retrieved from the TLB, without having to incur the costs associated with a page table walk. The retrieved physical address may then be used for accessing memory structures such as the shared memory or one or more caches which may be present between the processors and the shared memory.
A cache is a small, high speed memory structure which stores a limited number of frequently accessed data (and/or data determined to have high likelihood of future use) and offers a faster access path for the data stored in the cache, in comparison to the longer access times which may be incurred for accessing a backing storage location of the cache (e.g., another cache or the shared memory such as a main memory). While the cache may be indexed and tagged with physical addresses associated with the data stored therein (also referred to as a physical indexed physically tagged or “PIPT” cache), it may be beneficial to alternatively implement the cache as a memory structure which is indexed and tagged using virtual addresses (also referred to as a virtually indexed and virtually tagged or “VIVT” cache).
Since the VIVT cache may be accessed using the virtual addresses, a translation of the virtual addresses to physical addresses is not required to search the cache, and so the VIVT cache may offer a faster access time. However, in some cases, the VIVT cache may be made to appear as a PIPT cache to software, to avoid scenarios where an entire cache may be invalidated by software upon a translation change (e.g., pursuant to a context switch between applications which use different pages and correspondingly, different virtual to physical address translations) that might not even be relevant to the cache. However, conventional implementations of a VIVT cache which appears as a PIPT cache to software suffer from drawbacks. For example, each virtual address page may cover a physical address space which is greater than the size of a cache line of the cache. Accordingly, even if only a single entry of the TLB or a single page is to be invalidated for a given TLB invalidate operation, there are no efficient processes for determining which specific cache lines of the cache are to be correspondingly invalidated. Thus, in conventional implementations, in the case of a TLB invalidate operation, the entire VIVT cache is invalidated.
Some techniques attempt to mitigate the number of lines invalidated in a VIVT instruction cache (I-cache) by filtering invalidates using a TLB. In such cases, the VIVT I-cache lines associated with a TLB entry being displaced must be invalidated.